Test Components
Hardware and software tests can be performed on the following components:
- CPU - This test component identifies all processors installed in a system, captures any associated configuration information, and provides the ability to verify proper operation of these devices.
- Instruction and Register Test - This test manipulates all the general registers through arithmetic operations. The arithmetic operations are done with all combinations of the listed registers. Any failure may indicate the processor (CPU) may not fully function and may give incorrect results in applications.
- Speed Test - This test verifies the CPU is running at the correct clock speed. The test determines the clock speed at which the CPU is running and compares that speed to the expected speed. The test takes three samples and averages them out. The actual speed is calculated using the Time Stamp Counter Model Specific Register. The expected speed used in the comparison is read from the SMBios. To have passed, the processor (CPU) should have returned an actual speed value matching the processor's (CPU's) rated speed as provided in the Time Stamp Counter Model Specific Register.
- Real Time Clock Test - This test ensures that the Real Time Clock updates the system's CMOS time. Any failure could result in failures for time-dependent applications. To have passed, the Real Time Clock should have updated the system's CMOS time accurately.
- Fans - This test component checks the status of the system fans.
- Graphics - This test component identifies all graphic devices installed in a system, captures any associated configuration information such as the ASIC and Monitor types, and provides the ability to verify proper operation of these devices.
- Input Devices - This test component identifies keyboard, mouse and other input devices connected to the system.
- Memory - This test component identifies all memory modules installed in a system, captures any associated configuration information, and provides the ability to verify proper operation of these modules.
- Address Test / Walk Test - These tests verify the integrity of the address busses connecting the processor(s) to the memory modules. This is done by writing data to all possible addresses that have only one bit either set (1) or reset (0), having alternating bits set, having all bits high and having all bits low. The purpose of this test is to check for address lines that are either shorted to ground, shorted to a high voltage signal, shorted to other address lines, or floating (disconnected). These tests alone, however, may not indicate a hard failure.
- Noise Test - This test verifies memory integrity by writing the inverse of the current test address to the current test address. The current test address alternates between the start and the end of the current test block, incrementing or decrementing the address until the entire test block has been accessed. The purpose of this test is to check for address and data bus transition problems when these lines are forced high and low as rapidly as possible. A failure of this test indicates a failure of the DIMM.
- March Test - This test is similar to a true walk bit test and is able to detect the following: address faults, stuck-at faults, transition faults, coupling faults, and linked coupling faults. These types of faults occur when memory cells within a bit cell array affect the operation of nearby memory cells. In many cases, static type tests will not detect these failures. A failure of this test indicates a failure of the DIMM.
- Random Address / Cache Test - This test verifies memory integrity by running random patterns across a given test range. The addresses used to store the patterns are randomly selected and normalized to fit within the current test block. The purpose of this test is to detect intermittent memory problems that can be caused by temperature, variable clock speeds, variable voltages, signal timing, manufacturing faults, variable refresh rates, and decay. This test is also useful in detecting memory faults that may not be detected by other static tests. A failure of this test indicates a failure of the DIMM.
- Read Test - This test scans all available memory (even the memory used by the OS) to check for the ECC errors that have not been detected yet. This test takes two parameters: First: Percent of Memory Tested Here user has to enter the Percentage value of the memory that is to be tested. Second: Size of Each Block Here user has to give the size of each memory block of the percentage of memory mentioned above and the required range is mentioned as part of test parameters.
- DIMM Temperature Test - The test verifies the associated DIMM ( dual in-line memory module ), is running under specified temperature, the default minimum and maximum values are 20 and 90 degree celcius respectively.
- MEMBIST Test - For systems that support Fully Buffered DIMMs and MEMBIST test support in BIOS, this test verifies memory integrity by running random patterns across a given test range. This test is unique in that it is a Built In Self Test performed by the memory controller. The purpose of this test is to detect intermittent memory problems that can be caused by temperature, variable clock speeds, variable voltages, signal timing, manufacturing faults, variable refresh rates, and decay. This test is also useful in detecting memory faults that may not be detected by other static tests. When this test is run, the system will reboot and pass parameters to BIOS, which will set up the memory controller to execute this test. When completed, the BIOS will store any pass or fail info into NVRAM and SPD memory in the DIMMs. After rebooting again, Insight Diags will then allow the Memory Test Component to process the pass or fail info. A failure of this test indicates a failure of the DIMM.
- Miscellaneous - This test component gathers and displays information obtained from the computer's configuration memory (CMOS), BIOS data area, Interrupt Vector table and diagnostic component information.
- Modem - This test component identifies all modem devices installed in a system, captures any associated configuration information, and provides the ability to verify the proper operation of these devices.
- Parallel Port - This test component identifies all parallel devices installed in a system and captures any associated configuration information. If the parallel port is properly configured and the information is available to the operating system, the associated DMA, IRQ, and I/O ports are reported. This test component also provides the ability to verify proper operation of these devices.
- PCI Bus - This test component identifies all PCI devices installed in a system and provides the ability to verify proper PCI I/O operation to the devices.
- Rack - This test component gathers and displays information about the components of the blade infrastructure, such as rack and installed chassis. The information includes chassis type, product ID, manufacturer ID, serial number, temperature of different zones in the rack, status of installed fans in the system, subsystem firmware revisions, and more. The rack test component also provides multiple tests for verifying rack subsystem versions, EPROM devices, and installed fans.
- Rib - This test component identifies remote insight boards installed in a system and captures any associated configuration information. Remote insight board testing is only performed if drivers are installed during discovery.
- Serial Port - This test component identifies all serial devices installed in a system, captures any associated configuration information, and provides the ability to verify proper operation of these devices.
- Storage - This test component identifies storage devices connected to a system through IDE, USB, SCSI or a Fibre Channel network. Supported devices include:
- IDE hard disk drives
- Floppy diskette drives
- USB floppy drives
- USB CD-ROM
- USB Drivekey
- SCSI disk drives
- SCSI tape drives
- SATA Hard drives
- SAS Hard drives
- SCSI controllers
- RAID controllers
- SATA Controller
- SAS Controller
- Intelligent SCSI backplanes
- Intelligent external storage boxes
- ...etc
Controllers may be connected to the host through PCI, I2C or serial port. The component also captures any associated configuration information, and provides the ability to verify proper operation of these devices.
SCSI and IDE Drive Self Test: The offline self tests are actually performed by the drive itself using test capabilities embedded in the drive firmware. The Short Offline Self Test performs limited testing and threshold checking, while the Extended Offline Self Test also performs a complete surface analysis.
- System Management - This test component identifies Hotplug LED, I2C, LCD, CMOS, and ASM system management devices installed in a system and provides the ability to verify proper operation of these devices.
- USB - This test component identifies all USB devices installed in a system, captures any associated configuration information, and provides the ability to verify proper operation of these devices.
A list of available tests for each test component and a list of error codes can be accessed through the Test Component and Error Codes menu selections on the Help tab menu bar.